Conventionally, in the case of performing access to a storage apparatus including a plurality of banks, there is a known technique of distributing data between the plurality of banks and alternately accessing different banks so as to conceal a switching time required for a row address change (for example, see Patent Reference 1).
The following describes an image decoding apparatus disclosed in Patent Reference 1.
FIG. 1 shows a mapping example of image data on a memory of the conventional image decoding apparatus, where an encoded data buffer area, a frame memory 1, a frame memory 2, and a frame memory 3 are each distributed between two banks of a bank 0 and a bank 1. Each of the frame memories is made up of an area for a luminance signal and an area for a chrominance signal.
FIG. 2 shows an operation transition pattern in a memory control method of the conventional image decoding apparatus. As shown in FIG. 2, access to the encoded data buffer area and the frame memories 1 to 3 is performed by alternately accessing the bank 0 and the bank 1. Meanwhile, a row address change is performed in such a manner that a row address for the bank 0 is changed during a time period of immediately preceding access to the bank 1. By doing so, a wait time associated with a row address change can be concealed.
For instance, such a memory control operation that alternately accesses different banks is carried out under management of a single master apparatus, and maintained even between different types of access such as (a) a display image data read, (b) a reference image data read, (c) an encoded data read, (d) an encoded data write, and (e) a decoded image data write.
Patent Reference 1: Japanese Unexamined Patent Application Publication No. 08-65686